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| SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Rev. 02 -- 14 December 2004 Product data 1. General description The SC16C550B is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s. The SC16C550B is pin compatible with the ST16C550, TL16C550 and PC16C550, and it will power-up to be functionally equivalent to the 16C450. The SC16C550B also provides DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C550B operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature range, and is available in plastic DIP40, PLCC44 and LQFP48 packages. 2. Features s s s s s s s s s 5 V, 3.3 V and 2.5 V operation Industrial temperature range After reset, all registers are identical to the typical 16C450 register set Capable of running with all existing generic 16C450 software Pin compatibility with the industry-standard ST16C450/550, TL16C450/550, PC16C450/550 Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V 16 byte transmit FIFO 16 byte receive FIFO with error flags Programmable auto-RTS and auto-CTS x In auto-CTS mode, CTS controls transmitter x In auto-RTS mode, RxFIFO contents and threshold control RTS Automatic hardware flow control Software selectable Baud Rate Generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Independent receiver clock input Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: s s s s s s s s Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs s s s s s s s x 5, 6, 7, or 8-bit characters x Even, Odd, or No-Parity formats x 1, 112, or 2-stop bit x Baud generation (up to 3 Mbit/s) False start-bit detection Complete status reporting capabilities 3-State output TTL drive capabilities for bi-directional data bus and control bus Line Break generation and detection Internal diagnostic capabilities: x Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RI, DCD, DSR, DTR, RTS). 3. Ordering information Table 1: Ordering information Industrial: VCC = 2.5 V, 3.3 V or 5 V 10 %; Tamb = -40 C to +85 C. Type number SC16C550BIA44 SC16C550BIB48 SC16C550BIN40 Package Name PLCC44 LQFP48 DIP40 Description plastic leaded chip carrier; 44 leads plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic dual in-line package; 40 leads (600 mil) Version SOT187-2 SOT313-2 SOT129-1 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 2 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 4. Block diagram SC16C550B TRANSMIT FIFO REGISTERS D0-D7 IOR, IOR IOW, IOW RESET DATA BUS AND CONTROL LOGIC TRANSMIT SHIFT REGISTER TX INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER RX A0-A2 CS0, CS1, CS2 AS REGISTER SELECT LOGIC DDIS DTR RTS OUT1, OUT2 MODEM CONTROL LOGIC INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR INT TXRDY RXRDY CTS RI DCD DSR 002aaa585 XTAL1 RCLK XTAL2 BAUDOUT Fig 1. Block diagram. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 3 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 5. Pinning information 5.1 Pinning 42 DCD 44 VCC 41 DSR 40 CTS 1 NC 6 D4 5 D3 4 D2 3 D1 2 D0 D5 D6 D7 7 8 9 43 RI 39 RESET 38 OUT1 37 DTR 36 RTS 35 OUT2 RCLK 10 RX 11 NC 12 TX 13 CS0 14 CS1 15 CS2 16 BAUDOUT 17 SC16C550BIA44 34 NC 33 INT 32 RXRDY 31 A0 30 A1 29 A2 XTAL1 18 XTAL2 19 IOW 20 IOW 21 VSS 22 NC 23 IOR 24 IOR 25 DDIS 26 TXRDY 27 AS 28 002aaa582 Fig 2. PLCC44 pin configuration. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 4 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 40 DCD 42 VCC 39 DSR 38 CTS 48 NC NC D5 D6 D7 RCLK NC RX TX CS0 1 2 3 4 5 6 37 NC 47 D4 46 D3 45 D2 44 D1 43 D0 41 RI 36 NC 35 RESET 34 OUT1 33 DTR 32 RTS 31 OUT2 SC16C550BIB48 7 8 9 30 INT 29 RXRDY 28 A0 27 A1 26 A2 25 NC CS1 10 CS2 11 BAUDOUT 12 NC 13 XTAL1 14 XTAL2 15 IOW 16 IOW 17 VSS 18 IOR 19 IOR 20 NC 21 DDIS 22 TXRDY 23 AS 24 002aaa583 Fig 3. LQFP48 pin configuration. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 5 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs D0 1 D1 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 RCLK 9 RX 10 TX 11 CS0 12 CS1 13 CS2 14 BAUDOUT 15 XTAL1 16 XTAL2 17 IOW 18 IOW 19 VSS 20 002aaa584 40 VCC 39 RI 38 DCD 37 DSR 36 CTS 35 MR 34 OUT1 33 DTR SC16C550BIN40 32 RTS 31 OUT2 30 INT 29 RXRDY 28 A0 27 A1 26 A2 25 AS 24 TXRDY 23 DDIS 22 IOR 21 IOR Fig 4. DIP40 pin configuration. 5.2 Pin description Table 2: Symbol A2-A0 Pin description Pin PLCC44 LQFP48 DIP40 29, 30, 31 28 26, 27, 28 24 26, 27, I 28 25 I Register select. A2-A0 are used during read and write operations to select the UART register to read from or write to. Refer to Table 3 for register addresses and refer to AS description. Address strobe. When AS is active (LOW), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal select logic directly; when AS is HIGH, the register select and chip select signals are held at the logic levels they were in when the LOW-to-HIGH transition of AS occurred. Baud out. BAUDOUT is a 16x clock signal for the transmitter section of the UART. The clock rate is established by the reference oscillator frequency divided by a divisor specified in the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to RCLK. Type Description AS BAUDOUT 17 12 15 O 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 6 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 2: Symbol CS0, CS1, CS2 CTS Pin description...continued Pin PLCC44 LQFP48 DIP40 14, 15, 16 40 9, 10, 11 38 12, 13, I 14 36 I Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these three inputs select the UART. When any of these inputs are inactive, the UART remains inactive (refer to AS description). Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (CTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. This pin has no effect on the UART's transmit or receive operation. Data bus. Eight data lines with 3-State outputs provide a bi-directional path for data, control and status information between the UART and the CPU. Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (DCD) of the modem status register indicates that DCD has changed states since the last read from the modem status register. If the modem status interrupt is enabled when DCD changes levels, an interrupt is generated. Driver disable. DDIS is active (LOW) when the CPU is not reading data. When active, DDIS can disable an external transceiver. Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DSR) of the modem status register indicates DSR has changed levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR changes levels, an interrupt is generated. Data terminal ready. When active (LOW), DTR informs a modem or data set that the UART is ready to establish communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR is placed in the inactive level either as a result of a Master Reset, during loop mode operation, or clearing the DTR bit. Interrupt. When active (HIGH), INT informs the CPU that the UART has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register or an enabled modem status interrupt. INT is reset (deactivated) either when the interrupt is serviced or as a result of a Master Reset. Not connected. Type Description D7-D0 9-2 4-2, 47-43 40 8-1 I/O DCD 42 38 I DDIS DSR 26 41 22 39 23 37 O I DTR 37 33 33 O INT 33 30 30 O NC 1, 12, 23, 34 1, 6, 13, 21, 25, 36, 37, 48 34, 31 - - OUT1, OUT2 38, 35 34, 31 O Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to inactive the (HIGH) level as a result of Master Reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. Receiver clock. RCLK is the 16x baud rate clock for the receiver section of the UART. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. RCLK 10 5 9 I 9397 750 14446 Product data Rev. 02 -- 14 December 2004 7 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 2: Symbol IOR, IOR Pin description...continued Pin PLCC44 LQFP48 DIP40 24, 25 19, 20 21, 22 I Read inputs. When either IOR or IOR is active (LOW or HIGH, respectively) while the UART is selected, the CPU is allowed to read status information or data from a selected UART register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied to its inactive level (i.e., IOR tied LOW or IOR tied HIGH). Master Reset. When active (HIGH), RESET clears most UART registers and sets the levels of various output signals. Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a LOW to a HIGH level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. Request to send. When active, RTS informs the modem or data set that the UART is ready to receive data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive (HIGH) level either as a result of a Master Reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. This pin has no effect on the UART's transmit or receive operation. Receiver ready. Receiver direct memory access (DMA) signaling is available with RXRDY. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO control register bit 3 (FCR[3]). When operating in the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register, RXRDY is active (LOW). When RXRDY has been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (HIGH). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDY goes active (LOW); when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (HIGH). Serial data input. RX is serial data input from a connected communications device. Serial data output. TX is composite serial data output to a connected communication device. TX is set to the marking (HIGH) level as a result of Master Reset. Transmitter ready. Transmitter DMA signaling is available with TXRDY. When operating in the FIFO mode, one of two types of DMA signaling can be selected using FCR[3]. When operating in the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. Type Description RESET RI 39 43 35 41 35 39 I I RTS 36 32 32 O RXRDY 32 29 29 O RX TX 11 13 7 8 10 11 I O TXRDY 27 23 24 O VCC 9397 750 14446 44 42 40 Power 2.5 V, 3.3 V or 5 V supply voltage. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 8 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 2: Symbol VSS IOW, IOW Pin description...continued Pin PLCC44 LQFP48 DIP40 22 20, 21 18 16, 17 20 Power Ground voltage. Write inputs. When either IOW or IOW is active (LOW or HIGH, respectively) and while the UART is selected, the CPU is allowed to write control words or data into a selected UART register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied to its inactive level (i.e., IOW tied LOW or IOW tied HIGH). Crystal connection or External clock input. Crystal connection or the inversion of XTAL1 if XTAL1 is driven. 18, 19 I Type Description XTAL1 XTAL2[1] [1] 18 19 14 15 16 17 I O In sleep mode, XTAL2 is left floating. 6. Functional description The SC16C550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The SC16C550B is fabricated with an advanced CMOS process to achieve low drain power and high speed requirements. The SC16C550B is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of none in the 16C450. The SC16C550B is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C550B by the larger transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. In addition, the four selectable levels of FIFO trigger interrupt are provided for maximum data throughput performance, especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C550B is capable of operation up to 3 Mbit/s with a 48 MHz external clock input (at 5 V). 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 9 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.1 Internal registers The SC16C550B provides 12 internal registers for monitoring and control. These registers are shown in Table 3. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR). Register functions are more fully described in the following paragraphs. Table 3: A2 0 0 0 0 1 1 1 1 0 0 [1] [2] Internal registers decoding A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 READ mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM)[2] LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch WRITE mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register n/a n/a Scratchpad Register General register set (THR/RHR, IER/ISR, MCR/MSR, FCR/LSR, SPR)[1] Baud rate register set These registers are accessible only when LCR[7] is a logic 0. These registers are accessible only when LCR[7] is a logic 1. 6.2 FIFO operation The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. Table 4: Flow control mechanism INT pin activation 1 4 8 14 Negate RTS 1 4 8 14 Assert RTS 0 0 0 0 Selected trigger level (characters) 1 4 8 14 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 10 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.3 Autoflow control (see Figure 5) Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using UART 1 and UART 2 from a SC16C550B with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency. ACE1 SERIAL TO PARALLEL RCV FIFO FLOW CONTROL D7 to D0 PARALLEL TO SERIAL XMT FIFO FLOW CONTROL CTS RTS TX RX RTS CTS ACE2 PARALLEL TO SERIAL XMT FIFO FLOW CONTROL D7 to D0 SERIAL TO PARALLEL RCV FIFO FLOW CONTROL 002aaa048 RX TX Fig 5. Autoflow control (auto-RTS and auto-CTS) example. 6.3.1 Auto-RTS (see Figure 5) Auto-RTS data flow control originates in the receiver timing and control block (see Figure 1 "Block diagram.") and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 7), RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the de-assertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the RX FIFO is emptied by reading the receiver buffer register. When the trigger level is 14 (see Figure 8), RTS is de-asserted after the first data bit of the 16th character is present on the RX line. RTS is reasserted when the RX FIFO has at least one available byte space. 6.3.2 Auto-CTS (see Figure 5) The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent (see Figure 6). The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 11 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.3.3 Enabling autoflow control and auto-CTS Autoflow control is enabled by setting MCR[5] and MCR[1]. Table 5: MCR[5] 1 1 0 Enabling autoflow control and auto-CTS MCR[1] 1 0 X Selection auto RTS and CTS auto CTS disable 6.3.4 Auto-CTS and auto-RTS functional timing TX Start bits 0 to 7 Stop Start bits 0 to 7 Stop Start bits 0 to 7 Stop CTS 002aaa049 (1) When CTS is LOW, the transmitter keeps sending serial data out. (2) If CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but is does not send the next byte. (3) When CTS goes from HIGH to LOW, the transmitter begins sending data again. Fig 6. CTS functional timing waveforms. The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figure 7 and Figure 8. RX Start byte N Stop Start byte N + 1 Stop Start byte Stop RTS IOR (RD RBR) 1 2 N N+1 002aaa050 (1) N = RCV FIFO trigger level (1, 4, or 8 bytes). (2) The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section. Fig 7. RTS functional timing waveforms, RCV FIFO trigger level = 1, 4, or 8 bytes. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 12 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs RX byte 14 byte 15 RTS released after the first data bit of byte 16 Start byte 16 Stop Start byte 18 Stop RTS IOR (RD RBR) 002aaa051 (1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth byte. (2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more than one byte of space available. (3) When the receive FIFO is full, the first receive buffer register read re-asserts RTS. Fig 8. RTS functional timing waveforms, RCV FIFO trigger level = 14 bytes. 6.4 Hardware/software and time-out interrupts Following a reset, the transmitter interrupt is enabled, the SC16C550B will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be serviced prior to continuing operations. The ISR register provides the current singular highest priority interrupt only. Only after servicing the higher pending interrupt will the lower priority be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC16C550B FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1x, 1.5x, or 2x bit times. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 13 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.5 Programmable baud rate generator The SC16C550B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. The SC16C550B can support a standard data rate of 921.6 kbit/s. A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 48 MHz, as required for supporting a 3 Mbit/s data rate. The SC16C550B can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins (see Figure 9). Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see Table 6). XTAL1 XTAL2 XTAL1 XTAL2 X1 1.8432 MHz 1.5 k C1 22 pF C2 47 pF 002aaa586 X1 1.8432 MHz C1 22 pF C2 33 pF Fig 9. Crystal oscillator connection. The generator divides the input 16x clock by any divisor from 1 to 216 - 1. The SC16C550B divides the basic crystal or external clock by 16. The frequency of the BAUDOUT output pin is exactly 16x (16 times) of the selected baud rate (BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 6 shows selectable baud rates when using a 1.8432 MHz crystal. For custom baud rates, the divisor value can be calculated using the following equation: XTAL1 clock frequency Divisor (in decimal) = ---------------------------------------------------------serial data rate x 16 (1) 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 14 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Baud rates using 1.8432 MHz or 3.072 MHz crystal Using 3.072 MHz crystal Baud rate error Desired baud rate 50 75 0.026 0.058 110 134.5 150 300 600 1200 1800 0.69 2000 2400 3600 4800 7200 9600 19200 38400 2.86 Divisor for 16x clock 3840 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 1.23 0.628 0.312 0.026 0.034 Baud rate error Divisor for 16x clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 Table 6: Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Using 1.8432 MHz crystal 6.6 DMA operation The SC16C550B FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output pins. Tables 7 and 8 show this. Table 7: Effect of DMA mode on state of RXRDY pin DMA mode 0-to-1 transition when FIFO empties 1-to-0 transition when FIFO reaches trigger level, or time-out occurs Non-DMA mode 1 = FIFO empty 0 = at least 1 byte in FIFO Table 8: Effect of DMA mode on state of TXRDY pin DMA mode 1 = FIFO is full 0 = FIFO has at least 1 empty location Non-DMA mode 1 = at least 1 byte in FIFO 0 = FIFO empty 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 15 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.7 Loop-back mode The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the normal modem interface pins are disconnected and reconfigured for loop-back internally. MCR[0:3] register bits are used for controlling loop-back diagnostic testing. In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 3-2) control the modem RI and DCD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are used to control the modem CTS and DSR inputs, respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (see Figure 10). The CTS, DSR, DCD, and RI are disconnected from their normal modem control input pins, and instead are connected internally to DTR, RTS, OUT1 and OUT2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four Modem Status Register bits 4-7. The interrupts are still controlled by the IER. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 16 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs SC16C550B TRANSMIT FIFO REGISTERS D0-D7 IOR, IOR IOW, IOW RESET DATA BUS AND CONTROL LOGIC TRANSMIT SHIFT REGISTER TX INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER MCR[4] = 1 RX A0-A2 CS0, CS1 CS2 AS REGISTER SELECT LOGIC RTS DDIS CTS DTR MODEM CONTROL LOGIC DSR OUT1 INT TXRDY RXRDY INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR RI OUT2 DCD 002aaa587 XTAL1 RCLK XTAL2 BAUDOUT Fig 10. Internal loop-back mode diagram. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 17 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7. Register descriptions Table 9 details the assigned bit functions for the fifteen SC16C550B internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.10. Table 9: SC16C550B internal registers Bit 6 bit 6 bit 6 Bit 5 bit 5 bit 5 Bit 4 bit 4 bit 4 Bit 3 bit 3 bit 3 modem status interrupt RCVR trigger (MSB) FIFOs enabled divisor latch enable reserved RCVR trigger (LSB) FIFOs enabled reserved reserved DMA mode select INT priority bit 2 parity enable Bit 2 bit 2 bit 2 Bit 1 bit 1 bit 1 Bit 0 bit 0 bit 0 receive holding register FIFO enable INT status word length bit 0 DTR Set[2] XX XX 00 bit 7 bit 7 A2 A1 A0 Register Default[1] Bit 7 General Register 0 0 0 0 0 0 0 0 1 RHR THR IER receive transmit line status holding interrupt register XMIT FIFO reset INT priority bit 1 stop bits RCVR FIFO reset INT priority bit 0 word length bit 1 RTS 0 1 0 FCR 00 0 1 0 ISR 01 0 0 0 1 1 LCR 00 set break set parity even parity 1 0 0 MCR 00 auto flow loop back OUT2, INT control enable enable trans. empty RI bit 6 bit 6 bit 14 trans. holding empty DSR bit 5 bit 5 bit 13 break interrupt CTS bit 4 bit 4 bit 12 framing error DCD bit 3 bit 3 bit 11 OUT1 1 0 1 LSR 60 FIFO data error DCD bit 7 bit 7 bit 15 parity error RI bit 2 bit 2 bit 10 overrun error DSR bit 1 bit 1 bit 9 receive data ready CTS bit 0 bit 0 bit 8 1 1 0 0 [1] [2] [3] 1 1 0 0 0 1 0 1 MSR SPR Set[3] DLL DLM X0 FF XX XX Special Register The value shown represents the register's initialized HEX value; X = n/a. These registers are accessible only when LCR[7] = 0. The Special Register set is accessible only when LCR[7] is set to a logic 1. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 18 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the THR empty flag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C550B and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16x clock rate. After 7-12 clocks, the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. 7.2 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INT output pin. Table 10: Bit 7:4 3 Interrupt Enable Register bits description Description Not used. Modem Status Interrupt. Logic 0 = Disable the modem status register interrupt (normal default condition). Logic 1 = Enable the modem status register interrupt. 2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a fully assembled receive character is transferred from RSR to the RHR/FIFO, i.e., data ready, LSR[0]. Logic 0 = Disable the receiver line status interrupt (normal default condition). Logic 1 = Enable the receiver line status interrupt. 1 IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the THR is empty, and is associated with LSR[1]. Logic 0 = Disable the transmitter empty interrupt (normal default condition). Logic 1 = Enable the transmitter empty interrupt. 0 IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO has reached the programmed trigger level, or is cleared when the FIFO drops below the trigger level in the FIFO mode of operation. Logic 0 = Disable the receiver ready interrupt (normal default condition). Logic 1 = Enable the receiver ready interrupt. Symbol IER[7:4] IER[3] 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 19 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: * The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. * FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. * The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C550B in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). * * * * LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[1:4] will provide the type of errors encountered, if any. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. * LSR[7] will indicate any FIFO data errors. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 20 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode Mode 0 (FCR bit 3 = `0'): Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty transmit space is available in the Transmit Holding Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. Mode 1 (FCR bit 3 = `1'): Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO has at least one empty location. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. 7.3.2 FIFO mode Table 11: Bit 7-6 FIFO Control Register bits description Description RCVR trigger. These bits are used to set the trigger level for the receive FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 12. Not used; set to 00. Symbol FCR[7] (MSB), FCR[6] (LSB) FCR[5] (MSB), FCR[4] (LSB) FCR[3] 5-4 3 DMA mode select. Logic 0 = Set DMA mode `0' (normal default condition). Logic 1 = Set DMA mode `1' Transmit operation in mode `0': When the SC16C550B is in the 16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode `0': When the SC16C550B is in 16C450 mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there are no more characters in the receiver. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 21 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs FIFO Control Register bits description...continued Description Transmit operation in mode `1': When the SC16C550B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode `1': When the SC16C550B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. Table 11: Bit Symbol 2 FCR[2] XMIT FIFO reset. Logic 0 = No FIFO transmit reset (normal default condition). Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] RCVR FIFO reset. Logic 0 = No FIFO receive reset (normal default condition). Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable. Logic 0 = Disable the transmit and receive FIFO (normal default condition). Logic 1 = Enable the transmit and receive FIFO. This bit must be a `1' when other FCR bits are written to, or they will not be programmed. Table 12: FCR[7] 0 0 1 1 RCVR trigger levels FCR[6] 0 1 0 1 RX FIFO trigger level (bytes) 1 4 8 14 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 22 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.4 Interrupt Status Register (ISR) The SC16C550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However, it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the interrupt status bits. Table 13 "Interrupt source" shows the data values (bits 0-3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. Table 13: Priority level 1 2 2 3 4 Table 14: Bit 7:6 Interrupt source ISR[3] 0 0 1 0 0 ISR[2] 1 1 1 0 0 ISR[1] 1 0 0 1 0 ISR[0] 0 0 0 0 0 Source of the interrupt LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time-out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) Interrupt Status Register bits description Symbol ISR[7:6] Description FIFOs enabled. These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs are enabled. Logic 0 or cleared = default condition. Not used. INT priority bits 2-0. These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Table 13). Logic 0 or cleared = default condition. INT status. Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending (normal default condition). 5:4 3:1 ISR[5:4] ISR[3:1] 0 ISR[0] 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 23 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15: Bit 7 Line Control Register bits description Description Divisor latch enable. The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled (normal default condition). Logic 1 = Divisor latch and enhanced feature register enabled. 6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. Logic 0 = no TX break condition (normal default condition). Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. 5 LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format. Programs the parity conditions (see Table 16). Logic 0 = parity is not forced (normal default condition). LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data. LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data. 4 LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4] selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1s in the transmitted data. The receiver must be programmed to check the same format (normal default condition). Logic 1 = EVEN Parity is generated by forcing an even number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. 3 LCR[3] Parity enable. Parity or no parity can be selected via this bit. Logic 0 = no parity (normal default condition). Logic 1 = a parity bit is generated during the transmission, receiver checks the data and parity for transmission errors. 2 LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with the programmed word length (see Table 17). Logic 0 or cleared = default condition. 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Table 18). Logic 0 or cleared = default condition. Symbol LCR[7] 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 24 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs LCR[5] parity selection LCR[4] X 0 1 0 1 LCR[3] 0 1 1 1 1 Parity selection no parity ODD parity EVEN parity force parity `1' forced parity `0' Table 16: LCR[5] X 0 0 1 1 Table 17: LCR[2] 0 1 1 Table 18: LCR[1] 0 0 1 1 LCR[2] stop bit length Word length 5, 6, 7, 8 5 6, 7, 8 Stop bit length (bit times) 1 1-12 2 LCR[1:0] word length LCR[0] 0 1 0 1 Word length 5 6 7 8 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 25 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19: Bit 7 6 5 4 Modem Control Register bits description Symbol MCR[7] MCR[6] MCR[5] MCR[4] Description Reserved; set to `0'. Reserved; set to `0'. Auto flow control enable. Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, DCD, and RI are disconnected from the SC16C550B I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see Figure 10). In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts' sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. Logic 0 = Disable loop-back mode (normal default condition). Logic 1 = Enable local loop-back mode (diagnostics). 3 MCR[3] OUT2, INTx enable. Used to control the modem DCD signal in the loop-back mode. Logic 0 = Forces INT output to the 3-State mode. In the loop-back mode, sets OUT2 (DCD) internally to a logic 1. Logic 1 = Forces the INT output to the active mode. In the loop-back mode, sets OUT2 (DCD) internally to a logic 0. 2 MCR[2] OUT1. This bit is used in the Loop-back mode only. In the loop-back mode, this bit is used to write the state of the modem RI interface signal via OUT1. RTS Logic 0 = Force RTS output to a logic 1 (normal default condition). Logic 1 = Force RTS output to a logic 0. 0 MCR[0] DTR Logic 0 = Force DTR output to a logic 1 (normal default condition). Logic 1 = Force DTR output to a logic 0. 1 MCR[1] 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 26 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C550B and the CPU. Table 20: Bit 7 Line Status Register bits description Description FIFO data error. Logic 0 = No error (normal default condition). Logic 1 = At least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode, this bit is set to `1' whenever the transmit FIFO and transmit shift register are both empty. THR empty. This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. Break interrupt. Logic 0 = No break condition (normal default condition). Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. 3 LSR[3] Framing error. Logic 0 = No framing error (normal default condition). Logic 1 = Framing error. The receive character did not have a valid stop bit(s). In the FIFO mode, this error is associated with the character at the top of the FIFO. 2 LSR[2] Parity error. Logic 0 = No parity error (normal default condition). Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. 1 LSR[1] Overrun error. Logic 0 = No overrun error (normal default condition). Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. Symbol LSR[7] 5 LSR[5] 4 LSR[4] 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 27 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Line Status Register bits description...continued Description Receive data ready. Logic 0 = No data in receive holding register or FIFO (normal default condition). Logic 1 = Data has been received and is saved in the receive holding register or FIFO. Table 20: Bit 0 Symbol LSR[0] 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C550B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. Table 21: Bit 7 Modem Status Register bits description Description Data Carrier Detect. DCD (Active-HIGH, logical 1). Normally this bit is the complement of the DCD input. In the loop-back mode this bit is equivalent to the OUT2 bit in the MCR register. Ring Indicator. RI (Active-HIGH, logical 1). Normally this bit is the complement of the RI input. In the loop-back mode this bit is equivalent to the OUT1 bit in the MCR register. Data Set Ready. DSR (Active-HIGH, logical 1). Normally this bit is the complement of the DSR input. In loop-back mode this bit is equivalent to the DTR bit in the MCR register. Clear To Send. CTS. CTS functions as hardware flow control signal input if it is enabled via MCR[5]. The transmit holding register flow control is enabled/disabled by MSR[4]. Flow control (when enabled) allows starting and stopping the transmissions based on the external modem CTS signal. A logic 1 at the CTS pin will stop SC16C550B transmissions as soon as current character has finished transmission. Normally MSR[4] is the complement of the CTS input. However, in the loop-back mode, this bit is equivalent to the RTS bit in the MCR register. DCD [1] Logic 0 = No DCD change (normal default condition). Logic 1 = The DCD input to the SC16C550B has changed state since the last time it was read. A modem Status Interrupt will be generated. 2 MSR[2] RI [1] Logic 0 = No RI change (normal default condition). Logic 1 = The RI input to the SC16C550B has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. Symbol MSR[7] 6 MSR[6] 5 MSR[5] 4 MSR[4] 3 MSR[3] 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 28 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Modem Status Register bits description...continued Description DSR [1] Logic 0 = No DSR change (normal default condition). Logic 1 = The DSR input to the SC16C550B has changed state since the last time it was read. A modem Status Interrupt will be generated. Table 21: Bit 1 Symbol MSR[1] 0 MSR[0] CTS [1] Logic 0 = No CTS change (normal default condition). Logic 1 = The CTS input to the SC16C550B has changed state since the last time it was read. A modem Status Interrupt will be generated. [1] Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C550B provides a temporary data register to store 8 bits of user information. 7.10 SC16C550B external reset conditions Table 22: Register IER ISR LCR MCR LSR MSR FCR Table 23: Output TX RTS DTR RXRDY TXRDY Reset state for registers Reset state IER[7:0] = 0 ISR[7:1] = 0; ISR[0] = 1 LCR[7:0] = 0 MCR[7:0] = 0 LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR[7:4] = input signals; MSR[3:0] = 0 FCR[7:0] = 0 Reset state for outputs Reset state HIGH HIGH HIGH HIGH LOW 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 29 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 8. Limiting values Table 24: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Vn Tamb Tstg Ptot(pack) Parameter supply voltage voltage at any pin operating temperature storage temperature total power dissipation per package Conditions Min GND - 0.3 -40 -65 Max 7 VCC + 0.3 +85 +150 500 Unit V V C C mW 9. Static characteristics Table 25: DC electrical characteristics Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V or 5.0 V 10 %, unless otherwise specified. Symbol VIL(CK) VIH(CK) VIL VIH VOL Parameter LOW-level clock input voltage HIGH-level clock input voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage on all outputs[2] IOL = 5 mA (databus) IOL = 4 mA (other outputs) IOL = 2 mA (databus) IOL = 1.6 mA (other outputs) VOH HIGH-level output voltage IOH = -5 mA (databus) IOH = -1 mA (other outputs) IOH = -800 A (databus) IOH = -400 A (other outputs) ILIL ICL ICC Ci Rpu(int) [1] [2] Conditions Min -0.3 1.8 -0.3 1.6 1.85 1.85 f = 5 MHz 500 2.5 V Max 0.45 VCC 0.65 0.4 0.4 10 30 3.5 5 Min -0.3 2.4 -0.3 2.0 2.0 500 3.3 V Max 0.6 VCC 0.8 0.4 10 30 4.5 5 Min -0.5 3.0 -0.5 2.2 2.4 500 5.0 V Max 0.6 VCC 0.8 VCC 0.4 10 30 4.5 5 - Unit V V V V V V V V V V V V A A mA pF k LOW-level input leakage current clock leakage average power supply current input capacitance internal pull-up resistance Refer to Table 2 "Pin description" on page 6 for a listing of pins having internal pull-up resistors. Except for x2, VOL = 1 V typically. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 30 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 10. Dynamic characteristics Table 26: AC electrical characteristics Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V or 5.0 V 10 %, unless otherwise specified. Symbol t1w, t2w t3w t4w t5s t5h t6s t6h t6s' t6h t7d t7w t7h t7h' t8d t9d t11d t12d t12h t13d t13w t13h t14d t15d t16s t16h t17d t18d t19d t20d t21d t22d t23d t24d t25d t26d t27d 9397 750 14446 Parameter clock pulse duration clock frequency address strobe width address set-up time address hold time chip select set-up time to AS address hold time address set-up time chip select hold time IOR delay from chip select IOR strobe width chip select hold time from IOR address hold time IOR delay from address read cycle delay IOR to DDIS delay delay from IOR to data data disable time IOW delay from chip select IOW strobe width chip select hold time from IOW IOW delay from address write cycle delay data set-up time data hold time delay from IOW to output delay to set interrupt from Modem input delay to reset interrupt from IOR delay from stop to set interrupt delay from IOR to reset interrupt delay from start to set interrupt delay from IOW to transmit start delay from IOW to reset interrupt delay from stop to set RXRDY delay from IOR to reset RXRDY delay from IOW to set TXRDY Conditions Min 15 [1] 2.5 V Max 16 100 77 15 100 100 100 1 100 100 24 100 1 100 100 Min 13 35 5 5 5 0 10 0 10 26 0 5 10 20 10 20 0 10 25 20 5 8 - 3.3 V Max 32 35 26 15 33 24 24 1 29 45 24 45 1 45 45 Min 10 25 1 5 0 0 5 0 10 23 0 5 10 20 10 15 0 10 20 15 5 8 - 5.0 V Max 48 30 23 15 29 23 23 1 28 40 24 40 1 40 40 Unit ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rclk ns ns Rclk ns Rclk ns ns 45 5 5 10 0 [2] 10 0 10 25 pF load [2] 77 0 5 10 20 10 20 0 10 25 20 15 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 8 - (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 31 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 26: AC electrical characteristics...continued Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V or 5.0 V 10 %, unless otherwise specified. Symbol t28d tRESET N [1] [2] Parameter delay from start to reset TXRDY Reset pulse width baud rate divisor Conditions Min 100 1 2.5 V Max 8 Min 40 3.3 V Max 8 Min 40 5.0 V Max 8 - Unit Rclk ns 216 - 1 1 216 - 1 1 216 - 1 Rclk Applies to external clock, crystal oscillator max 24 MHz. Applicable only when AS is tied LOW. 10.1 Timing diagrams t4w AS t5s t5h A0-A2 VALID ADDRESS t6s t6h CS2 CS1-CS0 t7d t8d VALID t7w t7h t9d IOR, IOR ACTIVE t11d t11d DDIS ACTIVE t12d t12h D0-D7 DATA 002aaa331 Fig 11. General read timing when using AS signal. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 32 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs t4w AS t5s t5h A0-A2 VALID ADDRESS t6s t6h CS2 CS1-CS0 t13d t14d VALID t13w t13h t15d IOW, IOW ACTIVE t16s t16h D0-D7 DATA 002aaa332 Fig 12. General write timing when using AS signal. A0-A2 VALID ADDRESS VALID ADDRESS t7h t6s t7h t6s t7w CS ACTIVE ACTIVE t7w t9d IOR ACTIVE t12d t12h t12d t12h D0-D7 DATA 002aaa333 Fig 13. General read timing when AS is tied to GND. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 33 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs A0-A2 VALID ADDRESS VALID ADDRESS t7h t6s t7h t6s CS ACTIVE ACTIVE t13w t15d t13w IOW ACTIVE t16s t16h t16s t16h D0-D7 DATA 002aaa334 Fig 14. General write timing when AS is tied to GND. IOW ACTIVE t17d RTS DTR CHANGE OF STATE CHANGE OF STATE DCD CTS DSR t18d t18d CHANGE OF STATE CHANGE OF STATE INT ACTIVE ACTIVE ACTIVE t19d IOR ACTIVE ACTIVE ACTIVE t18d RI CHANGE OF STATE 002aaa347 Fig 15. Modem input/output timing. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 34 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs t2w EXTERNAL CLOCK t3w t1w 002aaa112 Fig 16. External clock timing. start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit RX 5 data bits 6 data bits 7 data bits INT t20d active t21d active IOR 16 baud rate clock 002aaa113 Fig 17. Receive timing. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 35 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs START BIT DATA BITS (5-8) PARITY BIT STOP BIT NEXT DATA START BIT RX D0 D1 D2 D3 D4 D5 D6 D7 t25d ACTIVE DATA READY t26d RXRDY IOR ACTIVE 002aaa578 Fig 18. Receive ready timing in non-FIFO mode. START BIT DATA BITS (5-8) PARITY BIT STOP BIT RX D0 D1 D2 D3 D4 D5 D6 D7 FIRST BYTE THAT REACHES THE TRIGGER LEVEL t25d ACTIVE DATA READY t26d RXRDY IOR ACTIVE 002aaa579 Fig 19. Receive ready timing in FIFO mode. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 36 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit TX 5 data bits 6 data bits 7 data bits INT t22d t23d IOW active active transmitter ready t24d active 16 baud rate clock 002aaa116 Fig 20. Transmit timing. START BIT DATA BITS (5-8) PARITY BIT STOP BIT NEXT DATA START BIT TX D0 D1 D2 D3 D4 D5 D6 D7 IOW ACTIVE D0-D7 BYTE #1 t28d t27d TXRDY ACTIVE TRANSMITTER READY TRANSMITTER NOT READY 002aaa580 Fig 21. Transmit ready timing in non-FIFO mode. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 37 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs START BIT DATA BITS (5-8) PARITY BIT STOP BIT TX D0 D1 D2 D3 D4 D5 D6 D7 5 DATA BITS 6 DATA BITS 7 DATA BITS IOW ACTIVE t28d D0-D7 BYTE #16 t27d TXRDY FIFO FULL 002aaa581 Fig 22. Transmit ready timing in FIFO mode (DMA mode `1'). 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 38 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 11. Package outline PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD y X A ZE eE 39 29 28 bp 40 b1 wM 44 HE A e A4 A1 (A 3) k 7 e D HD 17 ZD B vMB vM A 6 18 Lp detail X 1 pin 1 index E 0 5 scale 10 mm DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min. mm inches 4.57 4.19 0.51 0.25 0.01 3.05 0.12 0.53 0.33 0.81 0.66 HE k Lp 1.44 1.02 v 0.18 w 0.18 y 0.1 ZD(1) ZE(1) max. max. 2.16 2.16 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.63 0.59 0.63 0.59 45 o 0.180 0.02 0.165 0.021 0.032 0.656 0.656 0.05 0.013 0.026 0.650 0.650 0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION ISSUE DATE 99-12-27 01-11-14 Fig 23. PLCC44 (SOT187-2). 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 39 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 24. LQFP48 (SOT313-2). 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 40 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 seating plane D ME A2 A L A1 c Z e b1 b 40 21 MH wM (e 1) pin 1 index E 1 20 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.02 A2 max. 4 0.16 b 1.70 1.14 0.067 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) E (1) e 2.54 0.1 e1 15.24 0.6 L 3.60 3.05 0.14 0.12 ME 15.80 15.24 0.62 0.60 MH 17.42 15.90 0.69 0.63 w 0.254 0.01 Z (1) max. 2.25 0.089 52.5 51.5 2.067 2.028 14.1 13.7 0.56 0.54 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT129-1 REFERENCES IEC 051G08 JEDEC MO-015 JEITA SC-511-40 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 25. DIP40 (SOT129-1). 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 41 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 12. Soldering 12.1 Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. 12.2 Through-hole mount packages 12.2.1 Soldering by dipping or by solder wave Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 12.2.2 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 12.3 Surface mount packages 12.3.1 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all the BGA and SSOP-T packages 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 42 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.3.3 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 43 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 12.4 Package related soldering information Table 27: Mounting Through-hole mount Through-holesurface mount Surface mount Suitability of IC packages for wave, reflow and dipping soldering methods Package[1] DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[4] BGA, LBGA, LFBGA, SQFP, SSOP-T[5], TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[7], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP [1] [2] Soldering method Wave suitable[3] not suitable not suitable Reflow[2] - not suitable suitable Dipping suitable - - not suitable[6] suitable - suitable not recommended[7][8] not recommended[9] suitable suitable suitable - - - [3] [4] [5] [6] [7] [8] [9] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Hot bar soldering or manual soldering is suitable for PMFP packages. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 44 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 13. Revision history Table 28: Rev Date 02 20041214 Revision history CPCN Description Product data (9397 750 14446) Modifications: * 01 20040326 - There is no modification to the data sheet. However, reader is advised to refer to AN10333 (Rev. 02) "SC16CXXXB baud rate deviation tolerance" (9397 750 14411) that was released together with this revision. Product data (9397 750 11967) 9397 750 14446 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 45 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 14. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 14446 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 02 -- 14 December 2004 46 of 47 Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.5 6.6 6.7 7 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 7.6 7.7 7.8 7.9 7.10 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 9 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 10 Autoflow control (see Figure 5) . . . . . . . . . . . . 11 Auto-RTS (see Figure 5). . . . . . . . . . . . . . . . . 11 Auto-CTS (see Figure 5). . . . . . . . . . . . . . . . . 11 Enabling autoflow control and auto-CTS . . . . 12 Auto-CTS and auto-RTS functional timing . . . 12 Hardware/software and time-out interrupts. . . 13 Programmable baud rate generator . . . . . . . . 14 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 15 Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 16 Register descriptions . . . . . . . . . . . . . . . . . . . 18 Transmit (THR) and Receive (RHR) Holding Registers . . . . . . . . . . . . . . . . . . . . . 19 Interrupt Enable Register (IER) . . . . . . . . . . . 19 IER versus Receive FIFO interrupt mode operation . . . . . . . . . . . . . . . . . . . . . . . 20 IER versus Receive/Transmit FIFO polled mode operation . . . . . . . . . . . . . . . . . . . . . . . 20 FIFO Control Register (FCR) . . . . . . . . . . . . . 21 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Interrupt Status Register (ISR) . . . . . . . . . . . . 23 Line Control Register (LCR) . . . . . . . . . . . . . . 24 Modem Control Register (MCR) . . . . . . . . . . . 26 Line Status Register (LSR) . . . . . . . . . . . . . . . 27 Modem Status Register (MSR). . . . . . . . . . . . 28 Scratchpad Register (SPR) . . . . . . . . . . . . . . 29 SC16C550B external reset conditions . . . . . . 29 8 9 10 10.1 11 12 12.1 12.2 12.2.1 12.2.2 12.3 12.3.1 12.3.2 12.3.3 12.4 13 14 15 16 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . Through-hole mount packages . . . . . . . . . . . Soldering by dipping or by solder wave . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Surface mount packages . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 32 39 42 42 42 42 42 42 42 43 43 44 45 46 46 46 (c) Koninklijke Philips Electronics N.V. 2004. Printed in the U.S.A. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 December 2004 Document order number: 9397 750 14446 |
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